1. Field of the Invention
The present invention relates to yield analysis, and in particular, to a yield analysis method capable of distinguishing random defect yield losses and systematic failure causing yield losses.
2. Description of the Related Art
With multi-billion dollar semiconductor fabrication facilities experiencing increased time-to-market pressures, accurate yield analysis and rapid yield improvement are essential to achieve profitable production of integrated circuits. For maximum competitiveness, cost per die must be minimized while quickly elevating the manufacturing yield to an economically acceptable level.
As shown in FIG. 1, defect inspection data of a wafer is depicted as a wafer map. A wafer 10 has a plurality of arrays of IC devices or chips, wherein each dark color marker 11 represents a failed chip and each blank color marker 13 represents a good chip.
These yield losses may be the result of random defects or systematic failures.
Random defects are defined as any physical anomaly that causes a circuit to fail and include shorts or resistive paths or openings caused by particles, excess metal that bridges steep underlying contours causing shorts, photoresist splatters and flakes, weak spots in insulators, pinholes, openings due to step coverage problems, scratches, and others.
Systematic failures have an observable, non-random signature, possibly over time or spatial signature. Some systematic failures caused by mis-processing escape inline optical inspections in the fabrication process as well as during parametric testing. A prevalent example is the edge loss illustrated in FIG. 2A. The thickness of films deposited on the wafer is often well-controlled across the central portion of the wafer but poorly near the edge, resulting in wholesale die yield loss near the edge. As shown in FIG. 2B, the spatial distribution of defective dies has a repeated pattern when a defective reticle is used for photolithography. Parametric testing and inline inspection are typically performed on a sample basis and exclude edge dies. Hence, systematic failures such as edge losses and random defects are factors in die yield loss.
Quality control in integrated circuit (IC) fabrication has traditionally been based on overall summary data such as lot or wafer yield. These measures are adequate if the defective ICs are distributed randomly both within and across wafers in a lot. In practice, however, the defects often occur in clusters or display other systematic patterns. In general, these spatially clustered defects have assignable causes that can be traced to individual machines or to a series of process steps not meeting specified requirements.
The overall yield is conventionally decomposed into systematic limited yield and defect limited yield. The overall yield is the product of the systematic limited yield and the defect limited yield. However, there is no effective way to individually calculate systematic limited yield and defect limited yield from known overall yield data.
Hence, there is a need for routine monitoring of probe test data at the wafer map level to distinguish systematic failure-based yield losses from those caused by random defects.